71. Grams. S. Lin and you may J. B. Kuo, “Fringing-Caused Slim-Channel-Effect (FINCE) Related Capacitance Conclusion from Nanometer FD SOI NMOS Gizmos Using Mesa-Isolation Through three dimensional Simulation” , EDSM , Taiwan ,
72. J. B. Kuo, “Progression out of Bootstrap Techniques in Lower-Voltage CMOS Electronic VLSI Circuits for SOC Applications” , IWSOC , Banff, Canada ,
P. Yang, “Entrance Misalignment Effect Associated Capacitance Choices out-of a great 100nm DG FD SOI NMOS Product that have n+/p+ Poly Best/Bottom Entrance” , ICSICT , Beijing, Asia
73. Grams. Y. Liu, N. C. Wang and you will J. B. Kuo, “Energy-Successful CMOS Highest-Weight Driver Circuit to the Complementary Adiabatic/Bootstrap (CAB) Way of Lowest-Energy TFT-Lcd Program Programs” , ISCAS , Kobe, Japan ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Trend of 100nm FD SOI CMOS Gadgets that have HfO2 High-k Gate Dielectric Provided Vertical and you can Fringing Displacement Effects” , HKEDSSC , Hong kong ,
75. J. B. KUo, C. H. Hsu and you will C. P. Yang, “Gate-Misalignment Associated Capacitance Behavior of good 100nm DG SOI MOS Equipment that have Letter+/p+ Top/Base Door” , HKEDSSC , Hong-kong ,
76. Grams. Y. Liu, N. C. Wang and you can J. B. Kuo, “Energy-Successful CMOS High-Weight Rider Routine toward Complementary Adiabatic/Bootstrap (CAB) Technique for Reduced-Electricity TFT-Liquid crystal display System Programs” , ISCAS , Kobe, The japanese ,
77. H. P. Chen and you will J. B. Kuo, “A beneficial 0.8V CMOS TSPC Adiabatic DCVS Reasoning Routine to the Bootstrap Method getting Lowest-Electricity VLSI” , ICECS , Israel ,
B. Kuo, “A book 0
80. J. B. Kuo and H. P. Chen, “A minimal-Voltage CMOS Stream Driver toward Adiabatic and you can Bootstrap Strategies for Low-Energy System Software” , MWSCAS , Hiroshima, The japanese ,
83. Yards. T. Lin, E. C. Sunlight, and you may J. B. Kuo, “Asymmetric Door Misalignment Affect Subthreshold Qualities DG SOI NMOS Gizmos Offered Fringing Digital Field effect” , Electron Products and you can Point Symposium ,
84. J. B. Kuo, Elizabeth. C. Sunrays, and Meters. T. Lin, “Research regarding Entrance Misalignment Effect on the newest Endurance Voltage of Double-Door (DG) Ultrathin FD SOI NMOS Gizmos Having fun with a compact Design Provided Fringing Electronic Field effect” , IEEE Electron Devices for Microwave and you may Optoelectronic Apps ,
86. Elizabeth. Shen and you can J. 8V BP-DTMOS Blogs Addressable Recollections Phone Routine Produced from SOI-DTMOS Process” , IEEE Conference for the Electron Devices and Solid-state Circuits , Hong kong ,
87. P. C. Chen and you will J. B. Kuo, “ic Reasoning Routine Using a direct Bootstrap (DB) Technique for Lowest-current CMOS VLSI” , Worldwide Symposium to the Circuits and you will Systems ,
89. J. B. Kuo and you will S. C. Lin, “Lightweight Dysfunction Model to own PD SOI NMOS Products Offered BJT/MOS Impression Ionization for Spruce Circuits Simulation” , IEDMS , Taipei ,
ninety. J. B. Kuo and you will S. C. Lin, “Lightweight LDD/FD SOI CMOS Product Model Offered Opportunity Transportation and you can Self Temperature having Liven Routine Simulator” , IEDMS , Taipei ,
91. S. C. Lin and you can J. B. Kuo, “Fringing-Triggered Barrier Lowering (FIBL) Effects of 100nm FD SOI NMOS Gizmos with a high Permittivity Entrance Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Appointment Proc , Williamsburg ,
92. J. B. Kuo and you can S. C. Lin, “The latest Fringing Electric Field effect towards the Small-Station Impact Threshold Current from FD SOI NMOS Gizmos having LDD/Sidewall Oxide Spacer Construction” , Hong-kong Electron Products Conference ,
93. C. L. Yang and J. B. Kuo, “High-Heat Quasi-Saturation Brand of Highest-Current DMOS Power meet pretty kyrgyzstani women looking for men Gizmos” , Hong kong Electron Gizmos Conference ,
94. Elizabeth. Shen and you can J. B. Kuo, “0.8V CMOS Posts-Addressable-Thoughts (CAM) Mobile Ciurcuit that have a quick Tag-Examine Functionality Having fun with Vast majority PMOS Active-Threshold (BP-DTMOS) Technique Centered on Practical CMOS Technology having Lowest-Voltage VLSI Options” , In the world Symposium into the Circuits and Systems (ISCAS) Procedures , Arizona ,